A simulation apparatus simulating a device that functions by cooperation between hardware and software is conventionally known. The simulation apparatus includes an HW (Hardware) model that simulates hardware processing and a SW (software) model that simulates software processing. The simulation apparatus performs the simulation by utilizing the HW model and the SW model. The simulation apparatus performs serial processing by the HW model and the SW model so as to implement parallel processing of a hardware component and a software component included in a simulation target device (hereafter refer to as an “actual device”).
The simulation apparatus holds and manages time information as a simulation time for each of the HW model and the SW model in order to reproduce time elapsing and timing of the actual device.
The simulation time and elapsed time due to the computing by the simulation apparatus will be described with reference to FIG. 10. FIG. 10 (A) is a diagram showing an example of a time for each processing during actual operation of the actual device (or estimated time for each processing at the design stage). FIG. 10(B) is a diagram showing an example of the simulation time on the simulation apparatus. FIG. 10(C) is a diagram showing a time (hereafter refer to as a “real-time”) for simulating each processing of the actual device by utilizing the simulation apparatus.
As to an example of a processing time of the actual device, a processing time of the processing A is 1 ms, a processing time of the processing B is 2 ms, the processing time of the processing C is 1 ms, and the processing time of the processing D is 1 ms as shown in FIG. 10(A). The simulation apparatus allowing for the simulation time manages times for each processing in the actual device as the simulation times. Then, the processing time and the simulation time have the same value as shown in FIGS. 10(A) and 10(B).
When the simulation apparatus simulates each processing of the actual device, the processing time for controlling hardware resources of the simulation apparatus and the processing time for software controlling occur. Consequently, the real-time extends beyond the processing time of the actual device as shown in FIG. 10(C), thereby developing a delay in each processing.
In the prior art, when the SW model is set in a state for awaiting an interrupt from the HW model, the simulation apparatus executes a loop for the wait processing (hereafter refer to as an “idle loop”). Namely, the simulation apparatus executing the simulation has to allocate the hardware resources to the processing relating to the idling state of the SW model. As a result, the execution speed of the simulation decreases.
In the conventional scheme, resources of the host computer are allocated to execution of a busy loop on the idle loop of an Operating System (OS). While a period of the simulation time elapses until an interrupt occurs, the host computer consumes the hardware resources more than necessary, thereby degrading the execution performance for the simulation.
A problem of the conventional technique will be described with reference to FIG. 11. FIG. 11 shows a transition in the case that a simulation engine simulates by switching executable units between the SW model and the HW model both in the idling state according to the simulation time.
The simulation system waits (the idle loop is executed) until the simulation time elapses by the same time of the simulation time which elapses in the HW model side, and reproduces time elapsing and timing of the simulation target. Hence, there is a problem in the conventional simulation system that the host Central Processing Unit (CPU) consumes resources more than necessary in order to execute the idle loop in the SW model as necessary There is also a problem in the simulation system that overhead of the simulation engine occurs for switching of the executable unit. The resource consumption of the host CPU and the switching of the executable unit degrade the execution performance of the simulation.
In the conventional simulation system including information of the simulation time, the executable unit of the SW model and the executable unit of the HW model operate in parallel while the same simulation time elapses. The SW model has to execute simulation by the time which is equal to the simulation time required for occurrence of an interrupt from the HW model. However, since there is no operable task except the idle loop in the SW model side, the idle loop executes the loop processing until the simulation time elapses.
In the simulation of the idling state, there is a method (real-time OS simulation method) of reducing the load on the Operating System (OS) in the idling state by switching between the process relative time timer function and the real-time timer function, as a method of avoiding unnecessary load on the host computer. However, in the method, it is necessary to simulate the idling state by utilizing resources of the host computer and the real-time should elapse.